Oct. 17 2006 2:00PM

Oct. 17 2006 3:00PM

We present the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming(ILP).The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm. It is an equalization algorithm, suitable for modern communication systems (4G and behind). For the floating-point calculations required in the algorithm, logarithmic number system arithmetic libraries was used in the FPGA implementation.

Pravidelný seminář Rozhodování a řízení za neurčitosti. (Kontaktní osoba: Miroslav Kárný)