0342262 20240111140739.120100617235959.9 6 s. www cav_un_epca*0343971978-1-4244-6610-8237-242Los AlamitosIEEE2010 multithreading instruction set extensions microthreading LEON3 SPARC FPGA cav_un_auth*0101077 Daněk Martin Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0202863 Kafka Leoš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0261496 Sýkora Jaroslav Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. pdf http://library.utia.cas.cz/separaty/2010/ZS/danek-instruction set extensions for multi-threading in leon3.pdf FP7-ICT-215216 European Commission BE 7E08013 GA MŠk cav_un_auth*0254219 CEZ:AV0Z10750506 This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems. cav_un_auth*0261497 DDECS 2010 : 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems Vídeň 14.04.2010-16.04.2010 AT 2011 JC http://hdl.handle.net/11104/0185041 2010 pdf cav_un_epca*0343971 Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 978-1-4244-6610-8 237 242 Los Alamitos IEEE 2010