Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique

0346745 20240103193810.020100914235959.9 Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique 4 s. cav_un_epca*0347026978-0-7695-4179-2Proceedings of the International Conference on Field Programmable Logic and Applications336-339PiscatawayIEEE2010 FPGA Clock Gating Digital design System on Chip Multicore Embedded System Power consumption cav_un_auth*0101105 Heřmánek Antonín Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0218430 Kuneš Michal Zpracování obrazové informace Department of Image Processing ZOI ZOI UTIA-B Department of Image Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101213 Tichý Milan Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. http://library.utia.cas.cz/separaty/2010/ZS/kunes-reducing power consumption of an embedded dsp platform through the clock-gating technique.pdf 7H09005 GA MŠk cav_un_auth*0253180 CEZ:AV0Z10750506 The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique. cav_un_auth*0263761 20th International Conference on Field Programmable Logic and Applications Milano 31.08.2010-02.09.2010 IT 2011 JA http://hdl.handle.net/11104/0187684 2010 cav_un_epca*0347026 Proceedings of the International Conference on Field Programmable Logic and Applications 978-0-7695-4179-2 336 339 Piscataway IEEE 2010