0363078 20240103195435.220110913235959.9 000296062401223 10.1109/ICASSP.2011.5946817 4 s. cav_un_epca*0360081978-1-4577-0539-71657-1660PrahaIEEE2011 LDU decomposition directional forgetting hardware accelerator cav_un_auth*0202591 Bartosinski Roman Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. http://library.utia.cas.cz/separaty/2011/ZS/bartosinski-0363078.pdf JU100230 Artemis GA MŠk CZ 7H10001 GA MŠk CZ cav_un_auth*0272880 CEZ:AV0Z10750506 The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform. cav_un_auth*0272365 ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing Praha 22.05.2011-27.05.2011 CZ 2012 IN 1 http://hdl.handle.net/11104/0199178 2011 000296062401223 WOS cav_un_epca*0360081 ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing 978-1-4577-0539-7 1657 1660 Praha IEEE 2011