0376595 20240103200836.020120511235959.9 000312905700020 84864357161 10.1109/DDECS.2012.6219026 6 s. P cav_un_epca*0376594978-1-4673-1185-462-67Tallinn, ESTONIAIEEE2012Raik, J.Stopjaková, V.Jenihhin, M.Vierhaus, H., T.Pleskacz, W.Ubar, R. custom accelerators vector processing FPGA cav_un_auth*0261496 Sýkora Jaroslav Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0202591 Bartosinski Roman Zpracování signálů Department of Signal Processing ZS ZS UTIA-B G Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0202863 Kafka Leoš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101077 Daněk Martin Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0233557 Honzík P. CZ http://library.utia.cas.cz/separaty/2012/ZS/sykora-0376595.pdf 7H10001 GA MŠk CZ cav_un_auth*0272880 CEZ:AV0Z10750506 The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs, 400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology. cav_un_auth*0280917 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems Tallinn 18.04.2012-20.04.2012 EE 2013 JC 6 4 A 4a 20231122135035.0 PR http://hdl.handle.net/11104/0208954 2012 Soubory v repozitáři: sykora-0376595.pdf 84864357161 SCOPUS 000312905700020 WOS cav_un_epca*0376594 Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems 978-1-4673-1185-4 62 67 Tallinn, ESTONIA IEEE 2012 Raik, J. 340 Stopjaková, V. 340 Jenihhin, M. 340 Vierhaus, H., T. 340 Pleskacz, W. 340 Ubar, R. 340