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<bibitem type="C">   <ARLID>0380377</ARLID> <utime>20240103201159.9</utime><mtime>20120927235959.9</mtime>         <title language="eng" primary="1">In-circuit, Run-time Compiler of Finite State Machines for the UTIA EdkDSP Customizable Accelerators</title>  <specification> <page_count>2 s.</page_count> </specification>   <serial><ARLID>cav_un_epca*0380376</ARLID><ISBN>N</ISBN><title>Fourth Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications</title><part_num/><part_title>Design Tools Poster Session</part_title><page_num>32-33</page_num><publisher><place>Milano</place><name>Politecnico di Milano</name><year>2012</year></publisher><editor><name1>Silvano</name1><name2>Cristina</name2></editor><editor><name1>Agosta</name1><name2>Giovanni</name2></editor><editor><name1>Cardoso</name1><name2>Joao</name2></editor></serial>    <keyword>finite states machines</keyword>   <keyword>run-time compiler</keyword>   <keyword>hardware accelerator</keyword>    <author primary="1"> <ARLID>cav_un_auth*0101120</ARLID> <name1>Kadlec</name1> <name2>Jiří</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <institution>UTIA-B</institution> <full_dept>Department of Signal Processing</full_dept> <garant>G</garant>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source> <url>http://library.utia.cas.cz/separaty/2012/ZS/kadlec-in-circuit run-time compiler of finite state machines for the utia edkdsp customiyable accelerators.pdf</url> </source>        <cas_special> <project> <project_id>2C06008</project_id> <agency>GA MŠk</agency> <ARLID>cav_un_auth*0217826</ARLID> </project> <project> <project_id>7H10001</project_id> <agency>GA MŠk</agency> <country>CZ</country> <ARLID>cav_un_auth*0272880</ARLID> </project>  <abstract language="eng" primary="1">Presentation of technology enabling automation of generation, configuration and compilation of both software and hardware components for system with CPU core and specialized UTIA EkDSP hardware accelerators.</abstract>  <action target="EUR"> <ARLID>cav_un_auth*0283251</ARLID> <name>DATE 2012 - Design Automation and Test in Europe conference and exhibition</name> <place>Dresden</place> <dates>12.03.2012-16.03.2012</dates>  <country>DE</country> </action>   <reportyear>2013</reportyear>  <RIV>JC</RIV>      <num_of_auth>1</num_of_auth>  <presentation_type> PO </presentation_type> <unknown tag="mrcbC55"> JC </unknown> <inst_support> RVO:67985556 </inst_support>  <permalink>http://hdl.handle.net/11104/0211099</permalink>        <arlyear>2012</arlyear>       <unknown tag="mrcbU63"> cav_un_epca*0380376 Fourth Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications Design Tools Poster Session N 32 33 Milano Politecnico di Milano 2012 </unknown> <unknown tag="mrcbU67"> Silvano Cristina 340 </unknown> <unknown tag="mrcbU67"> Agosta Giovanni 340 </unknown> <unknown tag="mrcbU67"> Cardoso Joao 340 </unknown> </cas_special> </bibitem>