0380442 20240103201204.920121031235959.9 8 s. C cav_un_epca*0380441978-0-7695-4798-5600-607IzmirConference Publishing Services2012NiarSmail custom accelerators vector processing FPGA DSP cav_un_auth*0261496 Sýkora Jaroslav Zpracování signálů Department of Signal Processing ZS ZS UTIA-B G Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0202591 Bartosinski Roman Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101077 Daněk Martin Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0233557 Honzík P. CZ http://library.utia.cas.cz/separaty/2012/ZS/sykora-reducing instruction issue overheads in application-specific vector processors.pdf 7H10001 GA MŠk CZ cav_un_auth*0272880 Artemis JU 100230 Commission EU XE cav_un_auth*0283284 The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table. cav_un_auth*0283283 15th Euromicro Conference on Digital System Design Cesme 05.09.2012-08.09.2012 TR 2013 JC 5 PR http://hdl.handle.net/11104/0211153 2012 cav_un_epca*0380441 Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012 978-0-7695-4798-5 600 607 Izmir Conference Publishing Services 2012 Niar Smail 340