0380861 20240103201233.020121011235959.9 8 s. cav_un_epca*03808601844-9689Carpathian Journal of Electronic and Computer Engineering41 (2011)27-34 multithreading microthreading SPARC microarchitecture FPGA cav_un_auth*0101077 Daněk Martin Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0202863 Kafka Leoš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0261496 Sýkora Jaroslav Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. http://library.utia.cas.cz/separaty/2011/ZS/danek-0380861.pdf 7E08013 GA MŠk cav_un_auth*0254219 FP7-ICT-215216 European Commission BE The article describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. An architecture of the developed processor is presented and its key blocks described - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro and Virtex5 FPGAs. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is shown for a simple DSP computation typical for embedded systems. 2013 JC 4 4 A 4a 20231122135212.8 http://hdl.handle.net/11104/0211467 2011 Soubory v repozitáři: danek-0380861.pdf cav_un_epca*0380860 Carpathian Journal of Electronic and Computer Engineering Carpathian Journal of Electronic and Computer Engineering 1844-9689 Roč. 4 č. 1 2011 27 34