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<bibitem type="L">   <ARLID>0380874</ARLID> <utime>20240103201234.0</utime><mtime>20121011235959.9</mtime>         <title language="eng" primary="1">Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs</title>  <publisher> <pub_time>2012</pub_time> </publisher>    <keyword>smart camera</keyword>   <keyword>video surveillance</keyword>   <keyword>vector processing</keyword>   <keyword>FPGA</keyword>    <author primary="1"> <ARLID>cav_un_auth*0202591</ARLID> <name1>Bartosinski</name1> <name2>Roman</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101077</ARLID> <name1>Daněk</name1> <name2>Martin</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0261496</ARLID> <name1>Sýkora</name1> <name2>Jaroslav</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution> <full_dept>Department of Signal Processing</full_dept>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>        <cas_special> <project> <project_id>7H10001</project_id> <agency>GA MŠk</agency> <country>CZ</country> <ARLID>cav_un_auth*0272880</ARLID> </project> <project> <project_id>JU 100230</project_id> <agency>Artemis JU</agency> <country>XE</country> </project>  <abstract language="eng" primary="1">This demonstration shows an early prototype of low-level image processing to be used in an embedded smart camera, that is foreground detection and image segmentation. The example uses camera with resolution 640x480 pixels for input images processed at 100MHz in the FPGA. The input can be easily extended to higher resolutions. The processed output is displayed on LCD screen.</abstract>     <reportyear>2013</reportyear>  <RIV>JC</RIV>       <permalink>http://hdl.handle.net/11104/0211478</permalink>       <arlyear>2012</arlyear>       <unknown tag="mrcbU10"> 2012 </unknown> </cas_special> </bibitem>