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<bibitem type="C">   <ARLID>0382184</ARLID> <utime>20240103201404.7</utime><mtime>20121105235959.9</mtime>         <title language="eng" primary="1">Video Surveillance Application Based on Application Specific Vector Processors</title>  <specification> <page_count>8 s.</page_count> <media_type>C</media_type> </specification>   <serial><ARLID>cav_un_epca*0382183</ARLID><ISBN>978-2-9539987-2-6</ISBN><ISSN>1966-7116</ISSN><title>Proceedings of the 2012 Conference on Design &amp; Architectures for Signal &amp; Image Processing</title><part_num/><part_title/><page_num>248-255</page_num><publisher><place>Gières</place><name>Electronic Chips &amp; Systems design Initiative</name><year>2012</year></publisher><editor><name1>Morawiec</name1><name2>Adam</name2></editor><editor><name1>Hinderscheit</name1><name2>Jinnie </name2></editor></serial>    <keyword>video surveillance</keyword>   <keyword>smart camera</keyword>   <keyword>custom accelerators</keyword>   <keyword>vector processing</keyword>   <keyword>FPGA</keyword>    <author primary="1"> <ARLID>cav_un_auth*0202591</ARLID> <name1>Bartosinski</name1> <name2>Roman</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <institution>UTIA-B</institution> <garant>G</garant>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101077</ARLID> <name1>Daněk</name1> <name2>Martin</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0261496</ARLID> <name1>Sýkora</name1> <name2>Jaroslav</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution> <full_dept>Department of Signal Processing</full_dept>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0233557</ARLID> <name1>Honzík</name1> <name2>P.</name2> <country>CZ</country>  </author>   <source> <url>http://library.utia.cas.cz/separaty/2012/ZS/bartosinski-0382184.pdf</url> </source>        <cas_special> <project> <project_id>7H10001</project_id> <agency>GA MŠk</agency> <country>CZ</country> <ARLID>cav_un_auth*0272880</ARLID> </project>  <abstract language="eng" primary="1">Current video surveillance applications put higher demand both on processing power and personal privacy. This results in new video processing solutions being based on smart cameras. This paper presents a sample implementation of a system that implements core functions of a smart camera - motion detection and labelling - in an FPGA. The implementation is based on the data-flow ASVP platform extended with a number of selection operations that enable to implement constructs with conditional branching. Experimental performance results and power consumption data are presented for an actual implementation in the Xilinx SP605 board.</abstract>  <action target="WRD"> <ARLID>cav_un_auth*0284627</ARLID> <name>Conference on Design &amp; Architectures for Signal &amp; Image Processing</name> <place>Karlsruhe</place> <dates>23.10.2012-25.10.2012</dates>  <country>DE</country> </action>    <reportyear>2013</reportyear>  <RIV>JC</RIV>     <presentation_type> PR </presentation_type> <inst_support> RVO:67985556 </inst_support>  <permalink>http://hdl.handle.net/11104/0212479</permalink>        <arlyear>2012</arlyear>       <unknown tag="mrcbU63"> cav_un_epca*0382183 Proceedings of the 2012 Conference on Design &amp; Architectures for Signal &amp; Image Processing 978-2-9539987-2-6 1966-7116 248 255 Gières Electronic Chips &amp; Systems design Initiative 2012 </unknown> <unknown tag="mrcbU67"> Morawiec Adam 340 </unknown> <unknown tag="mrcbU67"> Hinderscheit Jinnie  340 </unknown> </cas_special> </bibitem>