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<bibitem type="L">   <ARLID>0384519</ARLID> <utime>20240103201637.5</utime><mtime>20121210235959.9</mtime>         <title language="cze" primary="1">DMA jednotka pro BCE v systémech s  AXI sběrnicí</title>  <publisher> <pub_time>2012</pub_time> </publisher>   <title language="eng" primary="0">BCE DMA unit for designs with AXI bus</title>    <keyword>AXI</keyword>   <keyword>DMA</keyword>   <keyword>BCE</keyword>   <keyword>worker</keyword>   <keyword>FPGA</keyword>   <keyword>Xilinx</keyword>    <author primary="1"> <ARLID>cav_un_auth*0101179</ARLID> <name1>Pohl</name1> <name2>Zdeněk</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <institution>UTIA-B</institution> <full_dept>Department of Signal Processing</full_dept>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source> <url>http://library.utia.cas.cz/separaty/2012/ZS/pohl-bce dma unit for designs with axi bus.pdf</url> </source>        <cas_special> <project> <project_id>7H10001</project_id> <agency>GA MŠk</agency> <country>CZ</country> <ARLID>cav_un_auth*0272880</ARLID> </project>  <abstract language="cze" primary="1">Hardwarovy modul zajistujici komunikaci pro BCE wokery v FPGA projektech s AXI sbernici.</abstract> <abstract language="eng" primary="0">Hardware IP core providing DMA functionality to the BCE workers in FPGA designs with AXI bus.</abstract>     <reportyear>2013</reportyear>  <RIV>IN</RIV>      <inst_support> RVO:67985556 </inst_support>  <permalink>http://hdl.handle.net/11104/0214142</permalink>        <arlyear>2012</arlyear>       <unknown tag="mrcbU10"> 2012 </unknown> </cas_special> </bibitem>