0391650 20240103202452.420130502235959.9 1 s. E cav_un_epca*0391649Grenoble2013 FPGA programmable accelerators computer video processing cav_un_auth*0101120 Kadlec Jiří Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. http://library.utia.cas.cz/separaty/2013/ZS/kadlec-edkdsp reprogrammable floating point accelerators on kintex fpga with hdmi.pdf 7H12004 GA MŠk CZ cav_un_auth*0290082 Presentation of the EdkDSP reprogrammable floating point accelerators on the Xilinx Kintex FPGA (KC705) together with the HDMI video I/O (ON Semiconductor Image sensor/HDMI 1080p60). Presented SoC is using the 512 bit wide AXI-4 buses and several independent VDMA controllers. cav_un_auth*0290577 DATE 2013 Design, Automation and Test in Europe Grenoble 2013.03.18-2013.03.22 FR 2014 JC 1 4 O 4o 20231122135603.4 PO http://hdl.handle.net/11104/0221083 1 2013 Soubory v repozitáři: 0391650.pdf cav_un_epca*0391649 2013 Design, Automation and Test in Europe Grenoble 2013