0410642 20240103182228.620060210235959.9 3-540-42499-7 Berlin Springer 2001 10 s. Lecture Notes in Computer Science. 2147 91-100BrebnerG.WoodsR. field programmable gate array cav_un_auth*0212813 Albu F. IE cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212755 Softley Ch. GB cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212571 Coleman J. N. GB cav_un_auth*0212814 Fagan A. IE 09G 09J HSLA 33544 ESPRIT XE AV0Z1075907 The LNS implementation of the LRLS algorithms in a FPGA offers better speed than C30/C40 DSP floating-point and provides low-cost, efficient solution for different system-on-chip applications. The resulting RLS Lattice cores operate with 24-bit precision fixed-point input/output signals. Therefore, the internal conversion to the log domain and the internal LNS operation can be hidden from the user. This presented work provides significant speedup without any loss of precision. cav_un_auth*0212815 International Conference FPL 2001 Belfast IE 27.08.2001-29.08.2001 JC ZS http://hdl.handle.net/11104/0130730 UTIA-B 20010111 2001 2001 Berlin Springer 3-540-42499-7 Field-Programmable Logic and Applications. Proceedings 91 100 Brebner G. 340 Woods R. 340