0410645 20240103182228.820060210235959.9 Nürnberg Design & Elektronik 2001 8 s. 547-554 field programmable gate array cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101152 Líčko Miroslav UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09J HSLA 33544 ESPRIT XE 212 HSLA Commission EC XE AV0Z1075907 Implementation of floatig point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core which implements these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. First, we describe Matlab library emulating bit-exactly the properties of the final hardware. cav_un_auth*0212816 Embedded Intelligence 2001 Nürnberg DE 14.02.2001-16.02.2001 JC ZS http://hdl.handle.net/11104/0130733 UTIA-B 20010114 2001 2001 Nürnberg Design & Elektronik Embedded Intelligence 2001 547 554