0410655 20240103182229.420060210235959.9 960-8052-39-4 Rethymno WSES Press 2001 5 s. 517-521MastorakisN. E.Pecorelli-PeresL. A. RLS Lattice logarithmic number system cav_un_auth*0212813 Albu F. IE cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212814 Fagan A. IE cav_un_auth*0212571 Coleman J. N. GB 09G HSLA 33544 ESPRIT XE AV0Z1075907 The LNS implementation of the Error-Feedback RLS Lattice algorithm in FPGA offers better speed than C30/C40 DSP floating-point and provides low- cost, efficient solution for different system on chip applications. We have demonstrated, that one can manage without a dedicated DSP processor. cav_un_auth*0212774 WSES International Conference on Circuits, Systems, Communications and Computers. CSCC 2001 /5./ Rethymno GR 08.07.2001-15.07.2001 JC ZS http://hdl.handle.net/11104/0130743 UTIA-B 20010124 2001 2001 Rethymno WSES Press 960-8052-39-4 Advances in Systems Science: Measurement, Circuits and Control. Proceedings 517 521 Mastorakis N. E. 340 Pecorelli-Peres L. A. 340