0410656 20240111140635.920060210235959.9 Abington Celoxica 2001 www field programmable gate array cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101152 Líčko Miroslav UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212755 Softley Ch. GB http://www.celoxica.com/programs/university/academic_papers.htm 202 kB 09G HSLA 33544 ESPRIT XE LN00B096 GA MŠk cav_un_auth*0027922 AV0Z1075907 Implementation of IEEE floating point in FPGA (Field Programmable Gate Array)is not easy and therefore many advanced DSP and control algorithms make it to FPGA with considerable delays. This paper presents one of possible solution based on a 32-bit logarithmic ALU, in the form of an FPGA core compatible with the Handel C 2.1 and the new DK1 tool from Celoxica. This research is performed under the EU ESPRIT 33544 HSLA Long-term research project, coordinated by the University of Newcastle. cav_un_auth*0212822 Celoxica User Conference /1./ Stratford GB 02.04.2001-04.04.2001 JC ZS http://hdl.handle.net/11104/0130744 UTIA-B 20010125 2001 2001 Abington Celoxica 202 kB Celoxica User Conference. Proceedings