0410672 20240103182230.720060210235959.9 80-7080-446-7 Praha VŠCHT 2001 5 s. 226-230ProcházkaA.UhlířJ. cav_un_auth*0101152 Líčko Miroslav UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. 09G HSLA 33544 ESPRIT XE AV0Z1075907 The article describes an algoritms development process for FPGA. It is shown on the example of the implementation of the QR RLS algorithm. To realise it means to perform operations such multiplication, division and square root.The research indicates, that the logarithmic arithemtic unit can reused for the real data type processing in some cases such a QR RLS algoritm.The developed prototype of logaritmic unit is tested on DSP algorithms using Matlab. cav_un_auth*0212830 MATLAB 2001 /9./ Praha CZ 11.10.2001 JC ZS http://hdl.handle.net/11104/0130760 UTIA-B 20010141 2001 2001 Praha VŠCHT 80-7080-446-7 Sborník příspěvků 9.ročníku konference MATLAB 2001 226 230 Procházka A. 340 Uhlíř J. 340