0410794 20240103182239.720060210235959.9 0-7695-1471-5 2 Designers Forum. Los Alamitos IEEE 2002 1 s. 271SciutoD.KloosC. D. logaritmic arithmetic core FPGA LNS cav_un_auth*0212890 Matoušek R. CZ cav_un_auth*0212891 Pohl Z. CZ cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101213 Tichý Milan UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09H LN00B096 GA MŠk cav_un_auth*0027922 CEZ:AV0Z1075907 Presentation of HW implementation of a complete Recursive Least Square (RLS) LATTICE core for Virtex XCV800 device. The computational parallelism and ease of pipelining of LATTICE leads to easy mapping on FPGA. Demonstration of the active noise cancellation with four 20-bit parallel Logarithic Arithemtic ALUs on the XESS HW with Virtex XCV800-4. cav_un_auth*0212892 Design, Automation and Test in Europe DATE 02 Paris FR 04.03.2002-08.03.2002 JC ZS http://hdl.handle.net/11104/0130881 UTIA-B 20020008 2002 2002 Los Alamitos IEEE 0-7695-1471-5 Design, Automation and Test in Europe DATE 02 271 Sciuto D. 340 Kloos C. D. 340