0410795 20240103182239.820060210235959.9 0-7695-1471-5 2 Designers˙Forum. Los Alamitos IEEE 2002 1 s. 264SciutoD.KloosC. D. logarithmic arithmetic matlab toolbox FPGA cores cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101213 Tichý Milan UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212891 Pohl Z. CZ cav_un_auth*0212893 Líčko M. CZ 09G 09H LN00B096 GA MŠk cav_un_auth*0027922 33544 ESPRIT XE CEZ:AV0Z1075907 The university booth presents Matlab tolbox, which supports two possible solutions for floating-point-like ALUs, based on a 32-bit and 20-bit logarithmic arithmetic. Both Virtex FPGA cores are encapsulated in function-like API interface compatible with DK1 tool from Celoxica (Handel C).DSP designers can create optimized VLIW program flow with 32-bit or 20-bit FP-like data range and precision. Code can be source-code-debugged and compiled from high-level to the target Virtex FPGA. cav_un_auth*0212894 Design, Automation and Test in Europe DATE˙02 Paris FR 04.03.2002-08.03.2002 JC ZS http://hdl.handle.net/11104/0130882 UTIA-B 20020009 2002 2002 Los Alamitos IEEE 0-7695-1471-5 Design, Automation and Test in Europe DATE˙02 264 Sciuto D. 340 Kloos C. D. 340