0410866 20240103182244.820060210235959.9 Praha FEL ČVUT 2002 1 s. 2 DSP FPGA floating-point cav_un_auth*0101152 Líčko Miroslav UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101213 Tichý Milan UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09H LN00B096 GA MŠk cav_un_auth*0027922 CEZ:AV0Z1075907 Poster describes an algorithm development process for FPGA. The process is shown on the example of an implementation of the QR RLS algorithm. cav_un_auth*0212938 International Student Conference on Electrical Engineering /6./ Praha CZ 23.05.2002 JC ZS http://hdl.handle.net/11104/0130953 UTIA-B 20020080 2002 2002 Praha FEL ČVUT POSTER 2002 2