Floating-Point-Like Arithmetic for FPGA

0410868 20240103182245.020060210235959.9 Floating-Point-Like Arithmetic for FPGA Praha FEL ČVUT 2002 1 s. POSTER 20022 HSLA, RLS, LNS IP core, DSP cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101152 Líčko Miroslav UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212939 Softley C. GB 09G 09H LN00B096 GA MŠk cav_un_auth*0027922 33544 ESPRIT XE CEZ:AV0Z1075907 In recent years we have investigated the use of a logarithmic number representation as an alternative to floating-point. Efficient techniques have been developed to facilitate arithmetic comparable to single precision floating-point in the logarithmic domain. cav_un_auth*0212938 International Student Conference on Electrical Engineering /6./ Praha CZ 23.05.2002 JC ZS http://hdl.handle.net/11104/0130955 UTIA-B 20020082 2002 2002 Praha FEL ČVUT POSTER 2002 2