Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic

0410916 20240103182248.520060210235959.9 0-7803-7403-7 Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic 3 Orlando IEEE 2002 4 s. Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing2681-2684 LNS, DSP, FPGA floating-point logarithmic arithmetic cav_un_auth*0212813 Albu F. IE cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212961 Coleman N. GB cav_un_auth*0212814 Fagan A. IE 09G 09H 33544 ESPRIT XE CEZ:AV0Z1075907 In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm on the Virtex FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solution based on 32-bit floating-point processors. cav_un_auth*0212908 ICASSP 2002 Orlando US 13.05.2002-17.05.2002 JC ZS http://hdl.handle.net/11104/0131003 UTIA-B 20020130 2002 2002 Orlando IEEE 0-7803-7403-7 Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing 2681 2684