Lattice adaptive filter implementation for FPGA

0411039 20240103182257.420060210235959.9 1-58113-651-X Lattice adaptive filter implementation for FPGA Monterey ACM 2003 1 s. FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays246 lattice adaptive filter FPGA cav_un_auth*0101179 Pohl Zdeněk UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101213 Tichý Milan UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0212893 Líčko M. CZ 09G 09H LN00B096 GA MŠk cav_un_auth*0027922 CEZ:AV0Z1075907 Our poster introduces an innovative RLS Lattice filter implementation for FPGAs. The signal processing applications typically require wide numeric range, and that poses a problem when using an FPGA implementation. Our aaproach is based on arithmetic using logarithmic numeric representation (LNS). The test application - adaptive noise canceller - has been optimized for the Xilinx Virtex devices. It consumes roughly 70% of all logic resources of the XCV800 device and all block memory cells. cav_un_auth*0213010 FPGA 2003 Monterey US 23.02.2003-25.02.2003 JC ZS http://hdl.handle.net/11104/0131126 UTIA-B 20030026 2003 2003 Monterey ACM 1-58113-651-X FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays 246