0411119 20240103182303.220060210235959.9 80-7083-708-X Liberec Technical University 2003 5 s. 294-298NouzaJ.DrábkováJ. FPGA runtine dynamic reconfiguration VHDL cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101077 Daněk Martin UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09H IST-2001-34016 EU IST XE cav_un_auth*0200683 CEZ:AV0Z1075907 Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way. cav_un_auth*0213048 ECMS 2003 /6./ Liberec CZ 02.06.2003-04.06.2003 JC ZS http://hdl.handle.net/11104/0131206 UTIA-B 20030106 2003 2003 Liberec Technical University 80-7083-708-X ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals 294 298 Nouza J. 340 Drábková J. 340