0411120 20240103182303.320060210235959.9 3-540-40822-3 Berlin Springer 2003 4 s. Lecture Notes in Computer Science. 2778 1095-1098CheungP. Y. K.ConstantinidesG. A.de SousaJ. D. FPGA logarithmic numbering system floating-point signal processor cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09H IST-2001-34016 EU IST XE cav_un_auth*0200683 LN00B096 GA MŠk cav_un_auth*0027922 CEZ:AV0Z1075907 This paper presents the FPGA implementation of a noise canceler with an adaptive RLS-Lattice filter in Xilinx devices. Since this algorithm requires floating-point computations, Logarithmic Numbering System (LNS) has been used. The pipelined lattice filter macro and input/output conversion routines has been designed. The implementation results are compared with an implementation on 32-bit IEEE floating-point signal processor. cav_un_auth*0213049 Field Programmable Logic and Applications /13./ Lisabon PT 01.09.2003-03.09.2003 JC ZS http://hdl.handle.net/11104/0131207 UTIA-B 20030107 2003 2003 Berlin Springer 3-540-40822-3 Field-Programmable Logic and Applications. Proceedings of the 13th International Conference 1095 1098 Cheung P. Y. K. 340 Constantinides G. A. 340 de Sousa J. D. 340