Using logarithmic arithmetic for FPGA implementation of the Givens rotations

0411123 20240103182303.520060210235959.9 84-8158-248-4 Using logarithmic arithmetic for FPGA implementation of the Givens rotations Vigo Universidade de Vigo 2003 6 s. Proceedings of the Sixth Baiona Workshop on Signal Processing in Communications199-204MosqueraC.Perez-GonzalesF. FPGA logarithmic arithmetic Givens rotations cav_un_auth*0101190 Schier Jan UTIA-B Department of Image Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101120 Kadlec Jiří UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09H IST-2001-34016 EU IST XE cav_un_auth*0200683 LN00B096 GA MŠk cav_un_auth*0027922 CEZ:AV0Z1075907 In this paper we describe an implementation of the Given rotations using the High speed logarithmic arithmetic (HSLA) library. This library is used for an efficient implementation of the floating-point arithmetic operation in FPGA (including the square root operation). The library was used to implement Given rotations in the Xilinx XCV2000E. The implementation was realised using some rapid prototyping tools for signal processing applications and for the FPGA design. cav_un_auth*0213053 Baiona Workshop on Signal Processing Communications /6./ Baiona ES 08.09.2003-10.09.2003 JC ZS http://hdl.handle.net/11104/0131210 UTIA-B 20030110 2003 2003 Vigo Universidade de Vigo 84-8158-248-4 Proceedings of the Sixth Baiona Workshop on Signal Processing in Communications 199 204 Mosquera C. 340 Perez-Gonzales F. 340