Logarithmic number system and floating-point arithmetics an FPGA

0411197 20240103182309.120060210235959.9 80-214-2471-0 Logarithmic number system and floating-point arithmetics an FPGA Brno VUT 2003 8 s. Počítačové Architektury & Diagnostika PAD 20039-16KotásekZ.RůžičkaR.SekaninaL. LNS arithmetic floating-point FPGA cav_un_auth*0101179 Pohl Zdeněk UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09H 33544 ESPRIT XE CEZ:AV0Z1075907 An introduction to a logarithmic number system (LNS) is presented. Range and procision of this arithmetic is briefly discussed. We show that the LNS arithmetics is suitable for a FPGA implementation. A case study will compare parameters of our LNS arithmetic library to a conventional floating-point arithmetic. cav_un_auth*0213111 PAD 2003 Počítačové Architektury & Diagnostika Zvíkovské Podhradí CZ 24.09.2003-26.09.2003 JC ZS http://hdl.handle.net/11104/0131283 UTIA-B 20030184 2003 2003 Brno VUT 80-214-2471-0 Počítačové Architektury & Diagnostika PAD 2003 9 16 Kotásek Z. 340 Růžička R. 340 Sekanina L. 340