0411198 20240103182309.120060210235959.9 80-214-2471-0 Brno VUT 2003 7 s. 17-23KotásekZ.RůžičkaR.SekaninaL. dynamic reconfiguration FPGA reconfiguration cycle cav_un_auth*0101159 Matoušek Rudolf UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. 09G 09H IST-2001-34016 Commission EC XE cav_un_auth*0200683 LN00B096 GA MŠk cav_un_auth*0027922 CEZ:AV0Z1075907 This paper discusses dynamic reconfiguration achievable using current FPGA methodology. An analysis of implementation issues has been presented and desirable features of future generation of CAD tools have been discussed. Several practical examples have been presented together with their implementation data. cav_un_auth*0213111 PAD 2003 Počítačové Architektury & Diagnostika Zvíkovské Podhradí CZ 24.09.2003-26.09.2003 JC ZS http://hdl.handle.net/11104/0131284 UTIA-B 20030185 2003 2003 Brno VUT 80-214-2471-0 Počítačové Architektury & Diagnostika PAD 2003 17 23 Kotásek Z. 340 Růžička R. 340 Sekanina L. 340