0411202 20240111140636.220060210235959.9 0-7695-1926-1 Los Alamitos IEEE Computer Society Press 2003 CD-ROM 1-6WernerB. high speed logarithmic arithmetic Matlab/Simulink rapid prototyping cav_un_auth*0101179 Pohl Zdeněk UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101190 Schier Jan UTIA-B Department of Image Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101152 Líčko Miroslav UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101105 Heřmánek Antonín UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101213 Tichý Milan UTIA-B Ústav teorie informace a automatizace AV ČR, v. v. i. 149 kB 09G 09H IST-2001-34016 Commission EC XE cav_un_auth*0200683 LN00B096 GA MŠk cav_un_auth*0027922 CEZ:AV0Z1075907 The paper is focused on the rapid prototyping for FPGA using the high-level environment of MATLAB/Simulink. An approach using the Xilinx system Generator is reviewed on an example of the High Speed Logaritmic Arithmetic unit. An alternative approach using the combination of the real time workshop with the Handel C compiler for automatized generation of the HDL code is presented. The possibilities to extend this solution in order to support the run-time reconfigurations are outlined. cav_un_auth*0213114 IEEE IPDPS 2003 Nice FR 22.04.2003-26.04.2003 JC ZS http://hdl.handle.net/11104/0131288 UTIA-B 20030189 2003 2003 Los Alamitos IEEE Computer Society Press 0-7695-1926-1 149 kB Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003 1 6 Werner B. 340