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<bibitem type="M">   <ARLID>0429947</ARLID> <utime>20240103204435.6</utime><mtime>20140819235959.9</mtime>    <DOI>10.1007/978-1-4614-8800-2</DOI>           <title language="eng" primary="1">The Architecture and the Technology Characterization  of an FPGA-Based Customizable Application-Speciﬁc  Vector Coprocessor (ASVP)</title>  <specification> <page_count>33 s.</page_count> <media_type>P</media_type> <book_pages>175</book_pages> </specification>   <serial><ARLID>cav_un_epca*0430588</ARLID><ISBN>978-1-4614-8799-9</ISBN><title>Smart Multicore Embedded Systems</title><part_num/><part_title/><page_num>45-77</page_num><publisher><place>New York</place><name>Springer</name><year>2014</year></publisher><editor><name1>Massimo</name1><name2>T.</name2></editor><editor><name1>Bertels</name1><name2>K.</name2></editor><editor><name1>Karlsson</name1><name2>S.</name2></editor><editor><name1>Pacull</name1><name2>F.</name2></editor></serial>    <keyword>custom accelerators</keyword>   <keyword>vector processing</keyword>   <keyword>FPGA</keyword>   <keyword>DSP</keyword>    <author primary="1"> <ARLID>cav_un_auth*0202591</ARLID> <name1>Bartosinski</name1> <name2>Roman</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101077</ARLID> <name1>Daněk</name1> <name2>Martin</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0202863</ARLID> <name1>Kafka</name1> <name2>Leoš</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution> <full_dept>Department of Signal Processing</full_dept>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0261496</ARLID> <name1>Sýkora</name1> <name2>Jaroslav</name2> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <institution>UTIA-B</institution>  <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source> <url>http://link.springer.com/chapter/10.1007/978-1-4614-8800-2_4</url> </source>        <cas_special> <project> <project_id>7H10001</project_id> <agency>GA MŠk</agency> <country>CZ</country> <ARLID>cav_un_auth*0272880</ARLID> </project>  <abstract language="eng" primary="1">The job of a computer architect is to build a bridge between what can be effectively built and what can be programmed effectively so that in the end application performance is optimized [1]. Indeed, in the last decade we have seen a wide deployment of parallel architectures in the form of chip-level scalar general-purpose multiprocessors (CMP) and streaming processors (GPU), but this was not met with a generally accepted solution to the problem of programming these systems in some unified manner. Examples of the programming interfaces include OpenMP, MPI (for CMPs), and OpenCL, CUDA (for GPUs). Thus we see that a compute architecture has to be designed in such a way to allow an efficient programming and applications development.</abstract>     <reportyear>2015</reportyear>  <RIV>JC</RIV>      <num_of_auth>5</num_of_auth>  <unknown tag="mrcbC52"> 4 A 4a 20231122140331.3 </unknown>  <permalink>http://hdl.handle.net/11104/0235497</permalink>   <confidential>S</confidential>        <arlyear>2014</arlyear>    <unknown tag="mrcbTft">  Soubory v repozitáři: bartosinski-0429947.pdf </unknown>    <unknown tag="mrcbU63"> cav_un_epca*0430588 Smart Multicore Embedded Systems 978-1-4614-8799-9 45 77 New York Springer 2014 </unknown> <unknown tag="mrcbU67"> Massimo T. 340 </unknown> <unknown tag="mrcbU67"> Bertels K. 340 </unknown> <unknown tag="mrcbU67"> Karlsson S. 340 </unknown> <unknown tag="mrcbU67"> Pacull F. 340 </unknown> </cas_special> </bibitem>