0448233 20240103210752.220151022235959.9 84963701840 000380507900041 10.1109/SAMOS.2015.7363690 5 s. E cav_un_epca*0448232978-1-4673-7311-1PiscatawayIEEE2015SoudrisDimitriosCarroLuigi floating point accelerators reconfigurability video processing programmable logic cav_un_auth*0101120 Kadlec Jiří UTIA-B Zpracování signálů Department of Signal Processing ZS ZS Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0306850 7H14004 GA MŠk This paper briefly describes basic Kintex7 FPGA video pipe infrastructure for UTIA demonstrator in the ARTEMIS JU project ALMARVI. The video pipeline is combined with the run-time reprogrammable vector floating point EdkDSP accelerators on the same FPGA chip. cav_un_auth*0320361 International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XV) 20.07.2015-23.07.2015 Agios Konstantinos, Samos GR JC 20000 20200 20206 2016 1 PR RVO:67985556 http://hdl.handle.net/11104/0250567 1 S RIV/67985556:_____/15:00448233!RIV16-AV0-67985556 191684524 Doplnění UT WOS RIV/67985556:_____/15:00448233!RIV16-MSM-67985556 191805902 Doplnění UT WOS 2015 84963701840 SCOPUS 000380507900041 WOS cav_un_epca*0448232 Proceedings 2015 International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XV) 978-1-4673-7311-1 Piscataway IEEE 2015 Soudris Dimitrios 340 Carro Luigi 340