0451496 20240103211318.120151201235959.9 2015 FPGA floating-point accelerator asymmetric multiprocessing ZYNQ Processing System cav_un_auth*0101120 Kadlec Jiří Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. http://sp.utia.cz/index.php?ids=results&id=emc2_amp_on_zynq_trenz_2015_2 7H14005 GA MŠk BE cav_un_auth*0308433 This application note describes the asymmetric multiprocessing design (AMP) based on the Xilinx application note XAPP1093. The AMP design is ported from ISE 14.5 design flow to the Xilinx Vivado 2015.2 and SDK 2015.2 design flow. The ARM Cortex A9 processor works together with the MicroBlaze processor, sharing the terminal and block ram. Both processors execute program from the same external DDR3 memory. The MicroBlaze processor is controlling 4 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by the PicoBlaze6 controller. 2016 JC http://hdl.handle.net/11104/0252656 S 2015 2015