0479509 20240103214705.520171013235959.9 85029518519 10.1007/978-3-319-66284-8 13 s. P cav_un_epca*0479508978-3-319-66283-10302-9743127-140ChamSpringer2017TonettaStefanoSchoitschErwinBitschFriedemann asymmetric multiprocessing Network-on-Chip Time-of-Flight sensor multi-core architectures cav_un_auth*0351450 Isakovic H. AT cav_un_auth*0351451 Grosu R. AT cav_un_auth*0351452 Ratasich D. AT cav_un_auth*0101120 Kadlec Jiří Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0351453 Kerrison S. GB http://library.utia.cas.cz/separaty/2017/ZS/kadlec-0479509.pdf cav_un_auth*0308433 7H14005 GA MŠk BE Technologies described in the paper provide hardware solution from architectural level up to the peripheral and application specific hardware. Moreover paper presents extendable multiprocessing hardware platform based on Zynq hybrid SoC, an asymmetric multiprocessing in video processing architecture, Time-of-Flight sensor and image processing architecture, predictable and verifiable Network-on-Chip (NoC), heterogeneous time-triggered NoC architecture, virtual hardware platform, software-driven energy consumption optimization techniques, and time-predictable L1 cache memory. The application of hybrid SoC platforms opposed to COTS multi-core architecture provides multiple benefits and can be seen as a viable bridging solution in the gap between single- and multi-core architectures. cav_un_auth*0351454 SAFECOMP 2017 International Conference on Computer Safety, Reliability, and Security 20170912 20170915 Trento IT JC 20000 20200 20206 2018 15 4 A hod 4ah 20231122142720.3 PR http://hdl.handle.net/11104/0276750 cav_un_auth*0320258 Vienna University of Technology AT cav_un_auth*0301841 University of Bristol GB 1 Department of Signal Processing UTIA-B 20206 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE S 0.328 Q2 Q2 2017 Soubory v repozitáři: kadlec-0479509.pdf 85029518519 SCOPUS PUBMED WOS cav_un_epca*0479508 Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS 978-3-319-66283-1 0302-9743 127 140 Cham Springer 2017 Lecture Notes in Computer Science 10489 340 Tonetta Stefano 340 Schoitsch Erwin 340 Bitsch Friedemann