0487427 20240103215717.720180305235959.9 2018 video processing HW acceleration programmable logic array cav_un_auth*0101120 Kadlec Jiří Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. http://sp.utia.cz/index.php?ids=results&id=t20i2tm4_things2do cav_un_auth*0307160 7H14007 GA MŠk BE The application note and evaluation package describes use of an evaluation package for the Xilinx SDK 2015.4 SW environment with these standalone, HW accelerated video processing demos designed in the Xilinx SDSoC 2015.4 environment. All demos work in parallel with single 8xSIMD EdkDSP run-time reprogrammable floating point accelerator IP developed within the ECSEL THINGS2DO project. All demos are designed for the Trenz Electronic TE0701-06 platform with industrial grade Zynq XC7Z020-2I device on System on Module TE0720-2IF. JC 20000 20200 20206 2018 3 http://hdl.handle.net/11104/0282553 S 2018 2018