0496948 20240103220948.720181122235959.9 2018 SDSoC system level compiler embedded C compiler HW acceleration programmable logic array cav_un_auth*0101120 Kadlec Jiří Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. http://sp.utia.cz/index.php?ids=results&id=TE0720_EdkDSP_2017_4_productive40 cav_un_auth*0359206 737459 EC This funkcional sample supports three Trenz Electronic Modules (TE0720-03-2IF, TE0720-03-1QF, TE0720-03-14S-1C) and two Trenz Electronic Carrier Boards (TE0703-05 and TE0706-02). The application note describes design of compact HW system based on Zynq all programmable 28nm chip with one or two Arm A9 processors and programmable logic area. System is optimised for Ethernet connected computing nodes serving for industrial automation, local data processing and data communication. The documented HW architecture is one of candidates for wider use within the ECSEL Productive 4.0 project for the edge computing node in the Industry 4.0 solutions. JC 20000 20200 20206 2019 3 4 A hod 4ah 20231122143608.8 http://hdl.handle.net/11104/0289572 1 Department of Signal Processing UTIA-B 20206 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE S 2018 Soubory v repozitáři: kadlec-0496948.pdf 2018