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<bibitem type="L">   <ARLID>0504521</ARLID> <utime>20240103222014.2</utime><mtime>20190514235959.9</mtime>         <title language="eng" primary="1">Arrowhead Compatible Zynq with SDSoC 2017.4 and Floating-Point 8xSIMD EdkDSP Accelerators</title>  <publisher> <pub_time>2019</pub_time> </publisher>    <keyword>Arrowhead Framework producer</keyword>   <keyword>Arrowhead Framework consumer</keyword>   <keyword>system level compiler</keyword>   <keyword>embedded C compiler</keyword>   <keyword>HW acceleration</keyword>   <keyword>programmable logic array</keyword>    <author primary="1"> <ARLID>cav_un_auth*0101120</ARLID> <name1>Kadlec</name1> <name2>Jiří</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101179</ARLID> <name1>Pohl</name1> <name2>Zdeněk</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source>  <url>http://sp.utia.cz/index.php?ids=results&amp;id=Zynq</url> </source>        <cas_special> <project> <ARLID>cav_un_auth*0359206</ARLID> <project_id>737459</project_id> <agency>EC</agency> <country>XE</country>  </project>  <abstract language="eng" primary="1">Design of compact HW system based on Zynq all programmable 28nm chip with one or two Arm A9 processors and programmable logic area. System is optimised for Ethernet connected computing nodes serving  for  industrial  automation,  local  data  processing  and  data  communication.  The  documented  HW architecture is one of candidates for wider use within the ECSEL Productive 4.0 project for the edge computing node inthe Industry 4.0 solutions. 2 carrier boards and 3 Zynq modules from Trenz Electronic are supported. Debian  image  is  provided  for  the  Zynq  board  in  format  of  image  for  the  SD  card.  Chapter  10  describes simple installtion of additionalSW  packages  and  templates  to  get  compatibility  with Arrowhead  framework G4.0  Java services.</abstract>     <RIV>JC</RIV> <FORD0>20000</FORD0> <FORD1>20200</FORD1> <FORD2>20206</FORD2>    <reportyear>2020</reportyear>       <num_of_auth>3</num_of_auth>   <permalink>http://hdl.handle.net/11104/0296325</permalink>   <confidential>S</confidential>        <arlyear>2019</arlyear>       <unknown tag="mrcbU10"> 2019 </unknown> </cas_special> </bibitem>