0507678 20240103222428.120190819235959.9 2019 system level compiler HW acceleration programmable logic array cav_un_auth*0101120 Kadlec Jiří Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. http://sp.utia.cz/index.php?ids=results&id=FitOptiVis-te0808-SDSoC-2018_2 cav_un_auth*0374054 8A18013 GA MŠk The functional sample describes FitOptiVis design time and run time resources supporting the Zynq Ultrascale+ board and Xilinx SDSoC 2018.2 system level compiler. The concrete board is Zynq Ultrascale+ TE0808-03-15EG-1EE. It works with large Xilinx XCZU15EG-1FFVC900E device with the quad core Arm A53 64 bit, dual Arm Cortex R5 and programmable logic area on single 16nm chip. The Zynq Ultrascale+ module has the 52 x 76 mm form factor. The Zynq Ultrascale+ board is designed and manufactured by company Trenz Electronic. JC 20000 20200 20206 2020 3 RVO:67985556 http://hdl.handle.net/11104/0298667 S 2019 2019