0507680 20240103222428.320190819235959.9 Video Input/Output IP Cores for TE0820 SoM with TE0701 Carrier and and Avnet HDMI Input/Output FMC Module 2019 system level compiler HW acceleration programmable logic array cav_un_auth*0225749 Kohout Lukáš Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101120 Kadlec Jiří Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. cav_un_auth*0101179 Pohl Zdeněk Zpracování signálů Department of Signal Processing ZS ZS UTIA-B Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. http://sp.utia.cz/index.php?ids=results&id=te0820-hio-ho cav_un_auth*0374054 8A18013 GA MŠk The functional sample describes video IP cores interfacing a video input and output of the Trenz TE0701-06 carrier board with TE0820-3EG SoM (System on Module based on Xilinx Zynq UltraScale+) and Avnet HDMI Input/Output FMC module. The system is designed with Xilinx Vivado 2018.3 tool (Web Pack edition). JC 20000 20200 20206 2020 3 RVO:67985556 http://hdl.handle.net/11104/0298665 S 2019 2019