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<bibitem type="L">   <ARLID>0543790</ARLID> <utime>20240103230006.6</utime><mtime>20210714235959.9</mtime>         <title language="eng" primary="1">DTRiMC tool for TE0808-15-EG-1EE module on TEBF0808 carrier board</title>  <publisher> <pub_time>2021</pub_time> </publisher>    <keyword>System on Chip</keyword>   <keyword>Zynq Ultrascale+</keyword>   <keyword>microprocessor</keyword>   <keyword>HW accelerated computing</keyword>   <keyword>automation</keyword>   <keyword>Linux Debian Stretch</keyword>    <author primary="1"> <ARLID>cav_un_auth*0101120</ARLID> <name1>Kadlec</name1> <name2>Jiří</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101179</ARLID> <name1>Pohl</name1> <name2>Zdeněk</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source> <url>http://sp.utia.cz/index.php?ids=results&amp;id=2018_2_te0808_fp03x8_4x2_ila_mulf64_DTRiMC</url>  </source>        <cas_special> <project> <project_id>8A18013</project_id> <agency>GA MŠk</agency> <ARLID>cav_un_auth*0374054</ARLID> </project>  <abstract language="eng" primary="1">Evaluation package with eight 8xSIMD, FP03x8, floating-point, run-time-reconfigurable accelerators for Zynq Ultrascale+ TE0808-15EG-1EE module on TEBF0808 carrier board. The TE0808-15EG-1EE module and TEBF0808 carrier board are designed and manufactured by the company Trenz Electronic. Xilinx device ZU15-EG-1EE device requires in the design phase Xilinx Vivado tools version 2018.2. These tools must have enabled support for the Xilinx ZU15-EG-1EE device. The Xilinx Vivado 2018.2 is currently the last Xilinx toolchain supporting the ZU15-EG-1EE device. The evaluation package provides several pre-compiled HW designs represented in form of SD-cards containing the designs and API interface for SW developer in form of shared Debian Linux libraries. The SW developer can program ARM host application in standard gcc or g++ compiler and “make” can be used for compilation of host applications directly on the embedded Zynq Ultrascale+ ZU15-EG-1EE based system.</abstract>     <RIV>JC</RIV> <FORD0>20000</FORD0> <FORD1>20200</FORD1> <FORD2>20206</FORD2>    <reportyear>2022</reportyear>       <num_of_auth>3</num_of_auth>   <permalink>http://hdl.handle.net/11104/0320986</permalink>   <confidential>S</confidential>        <arlyear>2021</arlyear>       <unknown tag="mrcbU10"> 2021 </unknown> </cas_special> </bibitem>