<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" href="style/detail_T.xsl"?>
<bibitem type="L">   <ARLID>0571124</ARLID> <utime>20240402213822.4</utime><mtime>20230424235959.9</mtime>         <title language="eng" primary="1">Xilinx Vitis AI facedetect and resnet50 Demo on Trenz Electronic TE0802 02 with ZU2CG and 1 GB LPDD4</title>  <publisher> <pub_time>2023</pub_time> </publisher>    <keyword>artificial intelligence</keyword>   <keyword>object detection</keyword>   <keyword>embedded systems</keyword>   <keyword>edge computing</keyword>   <keyword>Vitis AI 2.0</keyword>   <keyword>AMD-Xilinx</keyword>   <keyword>Zynq UltraScale+</keyword>    <author primary="1"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101179</ARLID> <name1>Pohl</name1> <name2>Zdeněk</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101120</ARLID> <name1>Kadlec</name1> <name2>Jiří</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source> <url>https://zs.utia.cas.cz/index.php?ids=results&amp;id=te0802_2cg_vitis_ai_resnet50</url>  </source>        <cas_special> <project> <project_id>8A21009</project_id> <agency>GA MŠk</agency> <ARLID>cav_un_auth*0432581</ARLID> </project>  <abstract language="eng" primary="1">A tutorial describing setup and run Vitis AI 2.0 facedetect and resnet50 demos on Trenz TE0802-02 board with ZU2CG and 1GB LPDD4. The system uses a Xilinx DPU unit to accelerate calculations. The DPU unit used in zcu104 or zcu102 does not fit into the used ZU2CG device. For this reason, a reduced DPU configuration is provided as well as precompiled models for demos. This text also describes how to move the system filesystem to the M.2 PCIe SSD.</abstract>     <RIV>JC</RIV> <FORD0>20000</FORD0> <FORD1>20200</FORD1> <FORD2>20206</FORD2>    <reportyear>2024</reportyear>       <num_of_auth>3</num_of_auth>   <permalink>https://hdl.handle.net/11104/0342451</permalink>   <confidential>S</confidential>        <arlyear>2023</arlyear>       <unknown tag="mrcbU10"> 2023 </unknown> </cas_special> </bibitem>