Fast Bayesian Algorithms for FPGA Platforms

0571273 20250526121246.720230502235959.9 Fast Bayesian Algorithms for FPGA Platforms QRD RLS Lattice algorithms FPGA parallel implementation HW accelerators cav_un_auth*0330517 Likhonina Raissa UTIA-B Zpracování signálů Department of Signal Processing ZS ZS CZ K Ústav teorie informace a automatizace AV ČR, v. v. i. http://library.utia.cas.cz/separaty/2023/ZS/likhonina-0571273.jpg 8A21009 GA MŠk cav_un_auth*0432581 101007321 ECSEL XE cav_un_auth*0450343 The abstract describes application of the QRD RLS Lattice algorithm for hand detection based on ultrasound and implemenation of the algorithm on FPGA platform. It discusses the results of implementation in terms of algorithm acceleration, computational time and MFLOP/s. DATE'23 (Design, Automation and Test in Europe Conference) 20230417 20230419 Antwerp BE https://www.date-conference.com/ cav_un_auth*0449374 JC 20000 20200 20205 2024 4 O 4o 20250526121246.7 PO RVO:67985556 https://hdl.handle.net/11104/0342937 S 2023 Soubory v repozitáři: 0571273.jpg SCOPUS PUBMED WOS