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<bibitem type="L">   <ARLID>0583418</ARLID> <utime>20240304105740.0</utime><mtime>20240229235959.9</mtime>         <title language="eng" primary="1">Support for TE0802-02-2AEV2-A board with Vitis AI 3.0 DPU and VGA display</title>  <publisher> <pub_time>2024</pub_time> </publisher>    <keyword>artificial intelligence</keyword>   <keyword>object detection</keyword>   <keyword>embedded systems</keyword>   <keyword>edge computing</keyword>   <keyword>Vitis AI 2.0</keyword>   <keyword>AMD-Xilinx</keyword>   <keyword>Zynq UltraScale+</keyword>    <author primary="1"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101120</ARLID> <name1>Kadlec</name1> <name2>Jiří</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101179</ARLID> <name1>Pohl</name1> <name2>Zdeněk</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source> <url>https://zs.utia.cas.cz/index.php?ids=results&amp;id=3_TE0802-02-2AEV2-A_AI_3_0_VGA</url>  </source>        <cas_special> <project> <project_id>9A23008</project_id> <agency>GA MŠk</agency> <country>CZ</country> <ARLID>cav_un_auth*0459137</ARLID> </project>  <abstract language="eng" primary="1">Tutorial how to design custom HW platform with AMD DPU for Vitis 2022.2 AI 3.0 inference in configuration B1024 and also with RGB video output to VGA display for Trenz Electronic evaluation board TE0802-02-2AEV2-A with AMD ZU2CG device.</abstract>       <reportyear>2025</reportyear>  <RIV>JC</RIV>    <FORD0>20000</FORD0> <FORD1>20200</FORD1> <FORD2>20206</FORD2>    <num_of_auth>3</num_of_auth>   <permalink>https://hdl.handle.net/11104/0351538</permalink>   <confidential>S</confidential>        <arlyear>2024</arlyear>       </cas_special> </bibitem>