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<bibitem type="L">   <ARLID>0617485</ARLID> <utime>20250313100604.4</utime><mtime>20250226235959.9</mtime>         <title language="eng" primary="1">Support for TE0820 Modules in Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G</title>  <publisher> <pub_time>2024</pub_time> </publisher>    <keyword>artificial intelligence</keyword>   <keyword>object detection</keyword>   <keyword>embedded systems</keyword>   <keyword>edge computing</keyword>   <keyword>Vitis AI 3.5</keyword>   <keyword>AMD-Xilinx</keyword>   <keyword>Zynq UltraScale+</keyword>    <author primary="1"> <ARLID>cav_un_auth*0101120</ARLID> <name1>Kadlec</name1> <name2>Jiří</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept language="eng">Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department language="eng">ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0101179</ARLID> <name1>Pohl</name1> <name2>Zdeněk</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0225749</ARLID> <name1>Kohout</name1> <name2>Lukáš</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author> <author primary="0"> <ARLID>cav_un_auth*0330517</ARLID> <name1>Likhonina</name1> <name2>Raissa</name2> <institution>UTIA-B</institution> <full_dept language="cz">Zpracování signálů</full_dept> <full_dept>Department of Signal Processing</full_dept> <department language="cz">ZS</department> <department>ZS</department> <full_dept>Department of Signal Processing</full_dept> <country>CZ</country> <fullinstit>Ústav teorie informace a automatizace AV ČR, v. v. i.</fullinstit> </author>   <source> <url>https://zs.utia.cas.cz/index.php?ids=results&amp;id=9_TE0820_AI_3_5</url>  </source>        <cas_special> <project> <project_id>9A23008</project_id> <agency>GA MŠk</agency> <country>CZ</country> <ARLID>cav_un_auth*0459137</ARLID> </project>  <abstract language="eng" primary="1">This tutorial describes support for systems based on TE0820 modules - how to design custom HW platform with AMD DPU for Vitis 2023.2 AI 3.5 runtime inference for family of Trenz Electronic modules TE0820 with AMD Zynq Ultrascale+ device.</abstract>     <RIV>JC</RIV> <FORD0>20000</FORD0> <FORD1>20200</FORD1> <FORD2>20206</FORD2>    <reportyear>2025</reportyear>       <num_of_auth>4</num_of_auth>   <permalink>https://hdl.handle.net/11104/0364820</permalink>   <confidential>S</confidential>        <arlyear>2024</arlyear>       <unknown tag="mrcbU10"> 2024 </unknown> </cas_special> </bibitem>