0618749 20260316111753.020250408235959.9 2025 AMD Versal AI Edge AMD Artix Chip2Chip HW IP block cav_un_auth*0225749 Kohout Lukáš UTIA-B Zpracování signálů Department of Signal Processing ZS ZS Department of Signal Processing Ústav teorie informace a automatizace AV ČR, v. v. i. https://zs.utia.cas.cz/index.php?ids=results&id=TE0950-Versal-Artix-communication 9A22004 GA MŠk CZ cav_un_auth*0459135 The TE0950 board from Trenz Electronic has two FPGA devices, AMD Versal™ AI Edge XCVE2302 in role of the main FPGA of the system and AMD Artix™ XC7A35T FPGA as configurable levelshifter/MUX for FMC and other 3.3 V IOs. These two FPGAs have dedicated up to 14 differential pairs to communicate with. This application note describes how to program the FPGAs and how to transfer AXI4 transaction between Versal™ and Artix™.The procedure described in this text is for a reference design from Trenz Electronic for 2023.2.2 tools. JC 20000 20200 20206 2026 1 https://hdl.handle.net/11104/0365897 S 2025 2025