| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0026328 |
| utime |
20240103181242.7 |
| mtime |
20060120235959.9 |
| title
(primary) (eng) |
Performance tuning of interative algorithms in signal processing |
| specification |
|
| serial |
| ISBN |
0-7803-9362-7 |
| title
|
Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005 |
| page_num |
699-702 |
| publisher |
| place |
Tampere |
| name |
Academy of Finland |
| year |
2005 |
|
| editor |
|
| editor |
|
| editor |
|
|
| title
(cze) |
Ladění výkonu iterativních algoritmů pro zpracování signálu |
| keyword |
signal processing |
| keyword |
FPGA |
| keyword |
high speed logarithmic arithmetic |
| author
(primary) |
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0202761 |
| name1 |
Šůcha |
| name2 |
P. |
| country |
CZ |
|
| author
|
| ARLID |
cav_un_auth*0202762 |
| name1 |
Hanzálek |
| name2 |
Z. |
| country |
CZ |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
1ET300750402 |
| agency |
GA AV ČR |
| country |
CZ |
| ARLID |
cav_un_auth*0001795 |
|
| project |
| project_id |
1M0567 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0202350 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
This paper presents high-level synthesis approach used to optimize computation speed of iterative DSP algorithms. It is based on cyclic scheduling method using formulation by ILP. |
| abstract
(cze) |
Navržený postup návrhu pro programovatelná logická pole nebo ASIC obvody umožňuje optimálně realizovat algoritmy pro zpracování signálu. Postup využívá schopností kompilátoru Handel-C vytvářet hardwarový popis algoritmu v závislosti na typu zadaného programovatelného obvodu. Navržený postup vychází ze zadání parametrů aritmetické jednotky použité pro výpočty a následném vyhledání optimálního rozvrhu operací pomocí celočíselného lineárního programování. |
| action |
| ARLID |
cav_un_auth*0202763 |
| name |
FPL 2005. International Conference on Field Programmable Logic and Applications |
| place |
Tampere |
| dates |
24.08.2005-26.08.2005 |
| country |
FI |
|
| reportyear |
2006 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0116596 |
| arlyear |
2005 |
| mrcbU63 |
Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005 0-7803-9362-7 699 702 Tampere Academy of Finland 2005 |
| mrcbU67 |
Rissa T. 340 |
| mrcbU67 |
Wilton S. 340 |
| mrcbU67 |
Leong P. 340 |
|