bibtype |
J -
Journal Article
|
ARLID |
0040181 |
utime |
20240111140638.5 |
mtime |
20060831235959.9 |
title
(primary) (eng) |
Implementing floating-point DSP |
specification |
|
serial |
title
|
Embedded Magazine |
volume_id |
2 |
volume |
3 (2006) |
page_num |
12-14 |
|
title
(cze) |
Implementace DSP v aritmetice s plovoucí řádovou čárkou |
keyword |
PicoBlaze |
keyword |
floating point |
keyword |
FPGA |
author
(primary) |
ARLID |
cav_un_auth*0101120 |
name1 |
Kadlec |
name2 |
Jiří |
institution |
UTIA-B |
full_dept |
Department of Signal Processing |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
author
|
ARLID |
cav_un_auth*0215906 |
name1 |
Chappel |
name2 |
S. |
country |
GB |
|
source |
|
COSATI |
09G |
COSATI |
09H |
cas_special |
project |
project_id |
1ET400750406 |
agency |
GA AV ČR |
ARLID |
cav_un_auth*0001796 |
|
project |
project_id |
1M0567 |
agency |
GA MŠk |
ARLID |
cav_un_auth*0202350 |
|
project |
project_id |
027611 |
agency |
EC |
country |
XE |
agency |
EC |
ARLID |
cav_un_auth*0225974 |
|
research |
CEZ:AV0Z10750506 |
abstract
(eng) |
In this article we demonstrate the use of PicoBlazeTM controllers for the assembly of high performance and power efficient floating point DSP pipelines. We decompose floating point algorithm into a sequence of hardware processes using a PicoBlazeTM network to manage the operation sequence. |
abstract
(cze) |
V článku je popsáno použití PicoBlaze procesorů pro implementaci DSP algoritmů v aritmetice s plovoucí řádovou čárkou na FPGA. |
reportyear |
2007 |
RIV |
JC |
permalink |
http://hdl.handle.net/11104/0133993 |
arlyear |
2006 |
mrcbU56 |
textový dokument |
mrcbU63 |
Embedded Magazine Roč. 2 č. 3 2006 12 14 |
|