bibtype C - Conference Paper (international conference)
ARLID 0040206
utime 20240103182634.1
mtime 20060802235959.9
title (primary) (eng) FPGA-based fault simulator
specification
page_count 5 s.
serial
ARLID cav_un_epca*0076660
ISBN 1-4244-0184-4
title Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems
page_num 274-278
publisher
place Prague
name Czech Technical University
year 2006
editor
name1 Reorda
name2 M. S.
editor
name1 Novák
name2 O.
editor
name1 Straube
name2 B.
title (cze) Simulátor chyb založený na programovatelném logickém obvodu
keyword falut simulation
keyword FPGA
keyword reconfiguartion
author (primary)
ARLID cav_un_auth*0202863
name1 Kafka
name2 Leoš
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0045825
name1 Novák
name2 O.
country CZ
COSATI 09G
COSATI 09H
cas_special
project
project_id 1QS108040510
agency GA AV ČR
ARLID cav_un_auth*0202864
research CEZ:AV0Z10750506
abstract (eng) This paper describes a simulator based an this technique and show that partial dynamic reconfiguration is an effective way of falut injection. Error-detection-code based CED circuits are used in experiments; the results of the experiments are reported.
abstract (cze) Článek presentuje simulátor chyb založený na programovatelném logickém poli.
action
ARLID cav_un_auth*0215912
name DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems
place Prague
dates 18.04.2006-21.04.2006
country CZ
reportyear 2007
RIV JC
permalink http://hdl.handle.net/11104/0134006
arlyear 2006
mrcbU63 cav_un_epca*0076660 Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems 1-4244-0184-4 274 278 Prague Czech Technical University 2006
mrcbU67 Reorda M. S. 340
mrcbU67 Novák O. 340
mrcbU67 Straube B. 340