| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0042476 |
| utime |
20240111140640.1 |
| mtime |
20061114235959.9 |
| title
(primary) (eng) |
FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic |
| specification |
| page_count |
6 s. |
| media_type |
CD-ROM |
|
| serial |
| ARLID |
cav_un_epca*0077005 |
| ISBN |
978-1-4244-0382-0 |
| ISBN |
1-4244-0383-9 |
| ISSN |
1520-6130 |
| title
|
Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation |
| page_num |
342-347 |
| publisher |
| place |
Calgary |
| name |
IEEE Signal Processing Society |
| year |
2006 |
|
| editor |
|
| editor |
|
|
| title
(cze) |
FPGA implementace adaptivních filtrů založených na GSFAP s využitím logaritmické aritmetiky |
| keyword |
adaptive filter |
| keyword |
DSP |
| keyword |
affine projection |
| keyword |
logarithmic arithmetic |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101213 |
| name1 |
Tichý |
| name2 |
Milan |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101190 |
| name1 |
Schier |
| name2 |
Jan |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0216190 |
| name1 |
Gregg |
| name2 |
D. |
| country |
IE |
|
| source |
| source_type |
textový soubor |
| source_size |
630 kB |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
MEIF-CT-2003-502085 |
| agency |
FP6 Marie Curie Intra European Fellowship |
| country |
BE |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
The paper deals with floating-point-like implementation of the GSFAP algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz. |
| abstract
(cze) |
Článek se zabývá implementací GSFAP algoritmu v plovoucí řádové čárce s využitím FPGA. Představuje optimalizovaný návrh GSFAP algoritmu implementovaný pomocí logaritmické aritmetiky, která se vyznačuje velice efektivním násobením a dělením. Výsledný hardware je schopen pracovat na hodinové frekvenci 80 MHz na čipu Xilinx XC2V1000-4. Hardware lze použít k realizaci adaptivních filtrů řádu 20 až 1000 schopných zpracovávat signály se vzorkovacím kmitočtem přesahujícím 50kHz. |
| action |
| ARLID |
cav_un_auth*0218758 |
| name |
IEEE Workshop on Signal Processing Systems Design and Implementation. 2006 |
| place |
Banff |
| dates |
02.10.2006-04.10.2006 |
| country |
CA |
|
| reportyear |
2010 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0003664 |
| arlyear |
2006 |
| mrcbU56 |
textový soubor 630 kB |
| mrcbU63 |
cav_un_epca*0077005 Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation 978-1-4244-0382-0 1520-6130 342 347 Calgary IEEE Signal Processing Society 2006 |
| mrcbU67 |
Badawy W. 340 |
| mrcbU67 |
Boumaiza S. 340 |
|