| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0042480 |
| utime |
20240103182852.2 |
| mtime |
20070419235959.9 |
| title
(primary) (eng) |
Using Reconfigurable HW for High Dimensional CAF Computation |
| specification |
|
| serial |
| ARLID |
cav_un_epca*0077006 |
| ISBN |
1-4244-0312-X |
| title
|
Proceeding 2006 International Conference on Field Programmable Logic and Applications |
| page_num |
641-644 |
| publisher |
| place |
Danvers |
| name |
Institute of Electrical and Electronic Engineering |
| year |
2006 |
|
| editor |
|
| editor |
|
| editor |
|
|
| title
(cze) |
Použití rekonfigurovatelného HW pro výpočet věrohodnostní funkce velkých rozměrů |
| keyword |
radio location |
| keyword |
CAF |
| keyword |
PCL |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0218430 |
| name1 |
Kuneš |
| name2 |
Michal |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0047818 |
| name1 |
Kvasnička |
| name2 |
M. |
| country |
CZ |
|
| COSATI |
09H |
| COSATI |
09G |
| COSATI |
09J |
| cas_special |
| project |
| project_id |
1M0567 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0202350 |
|
| project |
| project_id |
ONERA20030001 |
| agency |
GA MO |
| country |
CZ |
| ARLID |
cav_un_auth*0226849 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
Adaptive filters are used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. The GSFAP algorithm, discussed in this paper, is characterised by convergence superior to the popular NLMS, with only slightly higher complexity. The paper deals with floating-point-like implementation of algorithm using FPGA hardware. We present an optimised core for the GSFAP, built using logarithmic arithemtic which provides very low cost multiplication and division. The design is crafted to make efficient use of the pipelined logarithmic addition units. |
| abstract
(cze) |
Základním problémem pasivní koherentní lokace (PCL) je rychlý a přesný výpočet věrohodnostní funkce (CAF). Věrohodnostní funkce představuje výkonovou spektrální hustotu kroskorelační funkce mezi přímím a odraženým signálem. Pro realizaci PCL systému je proto nezbytné vyvynout HW akcelerátor pro výpočet CAF. Tento příspěvek presentuje návrh akcelerátoru pro PC pro výpočet CAF založeném na obvodech FPGA. Výsledky ukazují, že tento akcelerátor by mohl být použit pro výpočet CAF v reálném čase. |
| action |
| ARLID |
cav_un_auth*0218759 |
| name |
International Conference on Field Programmable Logic and Applications. 2006 |
| place |
Madrid |
| dates |
28.08.2006-30.08.2006 |
| country |
ES |
|
| reportyear |
2007 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0135694 |
| arlyear |
2006 |
| mrcbU63 |
cav_un_epca*0077006 Proceeding 2006 International Conference on Field Programmable Logic and Applications 1-4244-0312-X 641 644 Danvers Institute of Electrical and Electronic Engineering 2006 |
| mrcbU67 |
Koch A. 340 |
| mrcbU67 |
Leong P. 340 |
| mrcbU67 |
Boemo E. 340 |
|