bibtype K - Conference Paper (Czech conference)
ARLID 0045414
utime 20240103183136.1
mtime 20061205235959.9
title (primary) (eng) Simulink as Tool for Prototyping Reconfigurable Image Processing Applications
specification
page_count 5 s.
serial
ARLID cav_un_epca*0077055
ISBN 80-7080-616-8
title Technical computing Prague 2006. 14th annual conference proceedings
page_num 52-57
publisher
place Prague
name Humusoft
year 2006
editor
name1 Procházka
name2 A.
title (cze) Simulink jako nástroj pro vývoj rekonfigurovatelných aplikací
keyword image processing
keyword reconfigurable applications
keyword rapid prototyping
keyword FPGA
author (primary)
ARLID cav_un_auth*0101136
name1 Kovář
name2 Bohumil
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101190
name1 Schier
name2 Jan
institution UTIA-B
full_dept Department of Image Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0202610
name1 Zemčík
name2 P.
country CZ
author
ARLID cav_un_auth*0202611
name1 Herout
name2 A.
country CZ
author
ARLID cav_un_auth*0202612
name1 Beran
name2 V.
country CZ
COSATI 09G
COSATI 09H
cas_special
project
project_id 1ET400750408
agency GA AV ČR
country CZ
ARLID cav_un_auth*0001798
research CEZ:AV0Z10750506
abstract (eng) Our paper focuses on rapid prototyping and configuration tools for an embedded system. It will present novel concept of an image processing architecture based on interconnection of a programmable logical chip (FPGAs) with digital signal processor (DSP). In the paper, we shall outline a configuration tool tailored towards systems combining both DSP and FPGA, based on a configuration/programming scripting language and with a complex library of functions and modules for selected applications in signal and video processing.
abstract (cze) Článek představuje novou architekturu pro vývoj a implementaci aplikací zpracování obrazu. Systém se skládá z nástrojů pro rychlý vývoj aplikací - Simulinku, konfiguračních nástrojů převádějících popis Simulinkového modelu do tvaru vhodného pro implementaci na DSP a FPGA čipech.
action
ARLID cav_un_auth*0218625
name Technical computing Prague 2006 /14./
place Prague
dates 26.10.2006
country CZ
reportyear 2007
RIV JC
permalink http://hdl.handle.net/11104/0137943
arlyear 2006
mrcbU63 cav_un_epca*0077055 Technical computing Prague 2006. 14th annual conference proceedings 80-7080-616-8 52 57 Prague Humusoft 2006
mrcbU67 Procházka A. 340